b7b7676d67
Signed-off-by: ilmarkov <imarkov@redhat.com> Co-authored-by: ilmarkov <imarkov@redhat.com>
605 lines
21 KiB
Plaintext
605 lines
21 KiB
Plaintext
#pragma once
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#include <cuda.h>
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#include <cuda_bf16.h>
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#include <cuda_fp16.h>
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#include <cuda_runtime.h>
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#if defined(USE_ROCM)
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typedef __hip_bfloat16 nv_bfloat16;
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#endif
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#include <iostream>
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#include <array>
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#include <limits>
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#include <map>
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#include <unordered_map>
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#include <vector>
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namespace vllm {
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#define CUDACHECK(cmd) \
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do { \
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cudaError_t e = cmd; \
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if (e != cudaSuccess) { \
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printf("Failed: Cuda error %s:%d '%s'\n", __FILE__, __LINE__, \
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cudaGetErrorString(e)); \
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exit(EXIT_FAILURE); \
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} \
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} while (0)
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// Maximal number of blocks in allreduce kernel.
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constexpr int kMaxBlocks = 36;
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// Default number of blocks in allreduce kernel.
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#ifndef USE_ROCM
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const int defaultBlockLimit = 36;
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CUpointer_attribute rangeStartAddrAttr = CU_POINTER_ATTRIBUTE_RANGE_START_ADDR;
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#else
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const int defaultBlockLimit = 16;
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hipPointer_attribute rangeStartAddrAttr =
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HIP_POINTER_ATTRIBUTE_RANGE_START_ADDR;
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#endif
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// Counter may overflow, but it's fine since unsigned int overflow is
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// well-defined behavior.
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using FlagType = uint32_t;
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// Two sets of peer counters are needed for two syncs: starting and ending an
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// operation. The reason is that it's possible for peer GPU block to arrive at
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// the second sync point while the current GPU block haven't passed the first
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// sync point. Thus, peer GPU may write counter+1 while current GPU is busy
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// waiting for counter. We use alternating counter array to avoid this
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// possibility.
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struct Signal {
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alignas(128) FlagType start[kMaxBlocks][8];
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alignas(128) FlagType end[kMaxBlocks][8];
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alignas(128) FlagType _flag[kMaxBlocks]; // incremental flags for each rank
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};
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struct __align__(16) RankData {
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const void* ptrs[8];
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};
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struct __align__(16) RankSignals {
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Signal* signals[8];
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};
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// like std::array, but aligned
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template <typename T, int sz>
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struct __align__(alignof(T) * sz) array_t {
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T data[sz];
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using type = T;
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static constexpr int size = sz;
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};
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// use packed type to maximize memory efficiency
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// goal: generate ld.128 and st.128 instructions
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template <typename T>
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struct packed_t {
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// the (P)acked type for load/store
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using P = array_t<T, 16 / sizeof(T)>;
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// the (A)ccumulator type for reduction
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using A = array_t<float, 16 / sizeof(T)>;
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};
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#define DINLINE __device__ __forceinline__
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// scalar cast functions
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DINLINE float upcast_s(half val) { return __half2float(val); }
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template <typename T>
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DINLINE T downcast_s(float val);
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template <>
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DINLINE half downcast_s(float val) {
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return __float2half(val);
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}
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// scalar add functions
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// for some reason when compiling with Pytorch, the + operator for half and
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// bfloat is disabled so we call the intrinsics directly
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DINLINE half& assign_add(half& a, half b) {
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a = __hadd(a, b);
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return a;
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}
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DINLINE float& assign_add(float& a, float b) { return a += b; }
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#if (__CUDA_ARCH__ >= 800 || !defined(__CUDA_ARCH__))
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DINLINE float upcast_s(nv_bfloat16 val) { return __bfloat162float(val); }
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template <>
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DINLINE nv_bfloat16 downcast_s(float val) {
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return __float2bfloat16(val);
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}
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DINLINE nv_bfloat16& assign_add(nv_bfloat16& a, nv_bfloat16 b) {
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a = __hadd(a, b);
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return a;
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}
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#endif
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template <typename T, int N>
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DINLINE array_t<T, N>& packed_assign_add(array_t<T, N>& a, array_t<T, N> b) {
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#pragma unroll
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for (int i = 0; i < N; i++) {
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assign_add(a.data[i], b.data[i]);
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}
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return a;
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}
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template <typename T, int N>
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DINLINE array_t<float, N> upcast(array_t<T, N> val) {
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if constexpr (std::is_same<T, float>::value) {
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return val;
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} else {
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array_t<float, N> out;
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#pragma unroll
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for (int i = 0; i < N; i++) {
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out.data[i] = upcast_s(val.data[i]);
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}
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return out;
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}
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}
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template <typename O>
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DINLINE O downcast(array_t<float, O::size> val) {
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if constexpr (std::is_same<typename O::type, float>::value) {
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return val;
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} else {
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O out;
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#pragma unroll
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for (int i = 0; i < O::size; i++) {
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out.data[i] = downcast_s<typename O::type>(val.data[i]);
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}
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return out;
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}
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}
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#if !defined(USE_ROCM)
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static DINLINE void st_flag_release(FlagType* flag_addr, FlagType flag) {
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#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 700
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asm volatile("st.release.sys.global.u32 [%1], %0;" ::"r"(flag),
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"l"(flag_addr));
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#else
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asm volatile("membar.sys; st.volatile.global.u32 [%1], %0;" ::"r"(flag),
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"l"(flag_addr));
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#endif
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}
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static DINLINE FlagType ld_flag_acquire(FlagType* flag_addr) {
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FlagType flag;
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#if defined(__CUDA_ARCH__) && __CUDA_ARCH__ >= 700
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asm volatile("ld.acquire.sys.global.u32 %0, [%1];"
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: "=r"(flag)
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: "l"(flag_addr));
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#else
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asm volatile("ld.volatile.global.u32 %0, [%1]; membar.gl;"
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: "=r"(flag)
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: "l"(flag_addr));
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#endif
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return flag;
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}
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static DINLINE void st_flag_volatile(FlagType* flag_addr, FlagType flag) {
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asm volatile("st.volatile.global.u32 [%1], %0;" ::"r"(flag), "l"(flag_addr));
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}
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static DINLINE FlagType ld_flag_volatile(FlagType* flag_addr) {
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FlagType flag;
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asm volatile("ld.volatile.global.u32 %0, [%1];"
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: "=r"(flag)
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: "l"(flag_addr));
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return flag;
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}
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// This function is meant to be used as the first synchronization in the all
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// reduce kernel. Thus, it doesn't need to make any visibility guarantees for
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// prior memory accesses. Note: volatile writes will not be reordered against
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// other volatile writes.
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template <int ngpus>
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DINLINE void barrier_at_start(const RankSignals& sg, Signal* self_sg,
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int rank) {
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uint32_t flag = self_sg->_flag[blockIdx.x] + 1;
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if (threadIdx.x < ngpus) {
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auto peer_counter_ptr = &sg.signals[threadIdx.x]->start[blockIdx.x][rank];
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auto self_counter_ptr = &self_sg->start[blockIdx.x][threadIdx.x];
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// Write the expected counter value to peer and wait for correct value
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// from peer.
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st_flag_volatile(peer_counter_ptr, flag);
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while (ld_flag_volatile(self_counter_ptr) != flag);
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}
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__syncthreads();
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// use one thread to update flag
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if (threadIdx.x == 0) self_sg->_flag[blockIdx.x] = flag;
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}
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// This function is meant to be used as the second or the final
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// synchronization barrier in the all reduce kernel. If it's the final
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// synchronization barrier, we don't need to make any visibility guarantees
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// for prior memory accesses.
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template <int ngpus, bool final_sync = false>
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DINLINE void barrier_at_end(const RankSignals& sg, Signal* self_sg, int rank) {
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__syncthreads();
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uint32_t flag = self_sg->_flag[blockIdx.x] + 1;
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if (threadIdx.x < ngpus) {
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auto peer_counter_ptr = &sg.signals[threadIdx.x]->end[blockIdx.x][rank];
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auto self_counter_ptr = &self_sg->end[blockIdx.x][threadIdx.x];
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// Write the expected counter value to peer and wait for correct value from
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// peer.
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if constexpr (!final_sync) {
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st_flag_release(peer_counter_ptr, flag);
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while (ld_flag_acquire(self_counter_ptr) != flag);
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} else {
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st_flag_volatile(peer_counter_ptr, flag);
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while (ld_flag_volatile(self_counter_ptr) != flag);
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}
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}
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if constexpr (!final_sync) __syncthreads();
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// use one thread to update flag
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if (threadIdx.x == 0) self_sg->_flag[blockIdx.x] = flag;
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}
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#else
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template <int ngpus>
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DINLINE void barrier_at_start(const RankSignals& sg, Signal* self_sg,
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int rank) {
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uint32_t flag = self_sg->_flag[blockIdx.x] + 1;
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if (threadIdx.x < ngpus) {
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// simultaneously write to the corresponding flag of all ranks.
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// Latency = 1 p2p write
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__scoped_atomic_store_n(&sg.signals[threadIdx.x]->start[blockIdx.x][rank],
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flag, __ATOMIC_RELAXED, __MEMORY_SCOPE_SYSTEM);
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// wait until we got true from all ranks
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while (__scoped_atomic_load_n(&self_sg->start[blockIdx.x][threadIdx.x],
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__ATOMIC_RELAXED,
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__MEMORY_SCOPE_DEVICE) < flag);
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}
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__syncthreads();
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// use one thread to update flag
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if (threadIdx.x == 0) self_sg->_flag[blockIdx.x] = flag;
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}
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template <int ngpus, bool final_sync = false>
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DINLINE void barrier_at_end(const RankSignals& sg, Signal* self_sg, int rank) {
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__syncthreads();
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uint32_t flag = self_sg->_flag[blockIdx.x] + 1;
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if (threadIdx.x < ngpus) {
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// simultaneously write to the corresponding flag of all ranks.
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// Latency = 1 p2p write
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__scoped_atomic_store_n(&sg.signals[threadIdx.x]->end[blockIdx.x][rank],
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flag,
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final_sync ? __ATOMIC_RELAXED : __ATOMIC_RELEASE,
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__MEMORY_SCOPE_SYSTEM);
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// wait until we got true from all ranks
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while (
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__scoped_atomic_load_n(&self_sg->end[blockIdx.x][threadIdx.x],
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final_sync ? __ATOMIC_RELAXED : __ATOMIC_ACQUIRE,
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__MEMORY_SCOPE_DEVICE) < flag);
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}
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if constexpr (!final_sync) __syncthreads();
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// use one thread to update flag
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if (threadIdx.x == 0) self_sg->_flag[blockIdx.x] = flag;
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}
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#endif
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template <typename P, int ngpus, typename A>
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DINLINE P packed_reduce(const P* ptrs[], int idx) {
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A tmp = upcast(ptrs[0][idx]);
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#pragma unroll
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for (int i = 1; i < ngpus; i++) {
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packed_assign_add(tmp, upcast(ptrs[i][idx]));
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}
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return downcast<P>(tmp);
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}
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template <typename T, int ngpus>
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__global__ void __launch_bounds__(512, 1)
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cross_device_reduce_1stage(RankData* _dp, RankSignals sg, Signal* self_sg,
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T* __restrict__ result, int rank, int size) {
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using P = typename packed_t<T>::P;
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using A = typename packed_t<T>::A;
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// note: we don't reorder the address so the accumulation order is the same
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// for all ranks, ensuring bitwise identical results
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auto dp = *_dp;
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barrier_at_start<ngpus>(sg, self_sg, rank);
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// do the actual reduction
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for (int idx = blockIdx.x * blockDim.x + threadIdx.x; idx < size;
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idx += gridDim.x * blockDim.x) {
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((P*)result)[idx] = packed_reduce<P, ngpus, A>((const P**)&dp.ptrs[0], idx);
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}
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barrier_at_end<ngpus, true>(sg, self_sg, rank);
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}
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template <typename P>
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DINLINE P* get_tmp_buf(Signal* sg) {
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return (P*)(((Signal*)sg) + 1);
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}
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template <typename T, int ngpus>
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__global__ void __launch_bounds__(512, 1)
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cross_device_reduce_2stage(RankData* _dp, RankSignals sg, Signal* self_sg,
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T* __restrict__ result, int rank, int size) {
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int tid = blockIdx.x * blockDim.x + threadIdx.x;
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int stride = gridDim.x * blockDim.x;
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using P = typename packed_t<T>::P;
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using A = typename packed_t<T>::A;
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int part = size / ngpus;
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int start = rank * part;
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int end = rank == ngpus - 1 ? size : start + part;
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int largest_part = part + size % ngpus;
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const P* ptrs[ngpus];
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P* tmps[ngpus];
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#pragma unroll
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for (int i = 0; i < ngpus; i++) {
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int target = (rank + i) % ngpus;
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ptrs[i] = (const P*)_dp->ptrs[target];
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tmps[i] = get_tmp_buf<P>(sg.signals[target]);
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}
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auto tmp_out = tmps[0];
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barrier_at_start<ngpus>(sg, self_sg, rank);
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// stage 1: reduce scatter
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for (int idx = start + tid; idx < end; idx += stride) {
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tmp_out[idx - start] = packed_reduce<P, ngpus, A>(ptrs, idx);
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}
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barrier_at_end<ngpus>(sg, self_sg, rank);
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// stage 2: allgather. Note: it's important to match the tid between
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// the two stages, because visibility across devices is only guaranteed
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// between threads that have the same tid. If thread i computes the sum of
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// start + i in the first stage, then thread i also gathers start + i from
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// all ranks.
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for (int idx = tid; idx < largest_part; idx += stride) {
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#pragma unroll
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for (int i = 0; i < ngpus; i++) {
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int gather_from_rank = ((rank + i) % ngpus);
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if (gather_from_rank == ngpus - 1 || idx < part) {
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int dst_idx = gather_from_rank * part + idx;
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((P*)result)[dst_idx] = tmps[i][idx];
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}
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}
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}
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}
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using IPC_KEY = std::array<uint8_t, sizeof(cudaIpcMemHandle_t)>;
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static_assert(sizeof(IPC_KEY) == sizeof(cudaIpcMemHandle_t));
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static_assert(alignof(IPC_KEY) == alignof(cudaIpcMemHandle_t));
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class CustomAllreduce {
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public:
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int rank_;
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int world_size_;
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// Full NVLink or xGMI connection between GPUs.
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bool fully_connected_;
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RankSignals sg_;
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// Stores an map from a pointer to its peer pointers from all ranks.
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std::unordered_map<void*, RankData*> buffers_;
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Signal* self_sg_;
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// Stores rank data from all ranks. This is mainly for cuda graph purposes.
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// For cuda graph to work, all kernel arguments must be fixed during graph
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// capture time. However, the peer pointers are not known during graph
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// capture time. Therefore, during capture, we increment the rank data
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// pointer and use that as the argument to the kernel. The kernel arguments
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// are stored in graph_unreg_buffers_. The actual peer pointers will be
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// filled in at the memory pointed to by the pointers in
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// graph_unreg_buffers_ when the IPC handles are exchanged between ranks.
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//
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// The overall process looks like this:
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// 1. Graph capture.
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// 2. Each rank obtains the IPC handles for each addresses used during cuda
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// graph capture using get_graph_buffer_ipc_meta.
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// 3. (In Python) all gather the IPC handles.
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// 4. Obtain the peer pointers by opening the IPC handles, and store them in
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// the rank data array at corresponding positions.
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RankData *d_rank_data_base_, *d_rank_data_end_;
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std::vector<void*> graph_unreg_buffers_;
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// a map from IPC handles to opened IPC pointers
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std::map<IPC_KEY, char*> ipc_handles_;
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/**
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* Signals are an array of ipc-enabled buffers from all ranks.
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* For each of the buffer, the layout is as follows:
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* | -- sizeof(Signal) -- | ------ a few MB ----- |
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* The first section is for allreduce synchronization, and the second
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* section is for storing the intermediate results required by some
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* allreduce algos.
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*
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* Note: this class does not own any device memory. Any required buffers
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* are passed in from the constructor.
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*/
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CustomAllreduce(Signal** signals, void* rank_data, size_t rank_data_sz,
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int rank, int world_size, bool fully_connected = true)
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: rank_(rank),
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world_size_(world_size),
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fully_connected_(fully_connected),
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self_sg_(signals[rank]),
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d_rank_data_base_(reinterpret_cast<RankData*>(rank_data)),
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d_rank_data_end_(d_rank_data_base_ + rank_data_sz / sizeof(RankData)) {
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for (int i = 0; i < world_size_; i++) {
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sg_.signals[i] = signals[i];
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}
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}
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char* open_ipc_handle(const void* ipc_handle) {
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auto [it, new_handle] =
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ipc_handles_.insert({*((IPC_KEY*)ipc_handle), nullptr});
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if (new_handle) {
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char* ipc_ptr;
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CUDACHECK(cudaIpcOpenMemHandle((void**)&ipc_ptr,
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*((const cudaIpcMemHandle_t*)ipc_handle),
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cudaIpcMemLazyEnablePeerAccess));
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it->second = ipc_ptr;
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}
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return it->second;
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}
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std::pair<std::string, std::vector<int64_t>> get_graph_buffer_ipc_meta() {
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auto num_buffers = graph_unreg_buffers_.size();
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auto handle_sz = sizeof(cudaIpcMemHandle_t);
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std::string handles(handle_sz * num_buffers, static_cast<char>(0));
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std::vector<int64_t> offsets(num_buffers);
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for (int i = 0; i < num_buffers; i++) {
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auto ptr = graph_unreg_buffers_[i];
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void* base_ptr;
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// note: must share the base address of each allocation, or we get wrong
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// address
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if (cuPointerGetAttribute(&base_ptr, rangeStartAddrAttr,
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(CUdeviceptr)ptr) != CUDA_SUCCESS)
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throw std::runtime_error("failed to get pointer attr");
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CUDACHECK(cudaIpcGetMemHandle(
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(cudaIpcMemHandle_t*)&handles[i * handle_sz], base_ptr));
|
|
offsets[i] = ((char*)ptr) - ((char*)base_ptr);
|
|
}
|
|
return std::make_pair(handles, offsets);
|
|
}
|
|
|
|
void check_rank_data_capacity(size_t num = 1) {
|
|
if (d_rank_data_base_ + num > d_rank_data_end_)
|
|
throw std::runtime_error(
|
|
"Rank data buffer is overflowed by " +
|
|
std::to_string(d_rank_data_base_ + num - d_rank_data_end_));
|
|
}
|
|
|
|
/**
|
|
* Register already-shared IPC pointers.
|
|
*/
|
|
void register_buffer(void** ptrs) {
|
|
check_rank_data_capacity();
|
|
RankData data;
|
|
for (int i = 0; i < world_size_; i++) {
|
|
data.ptrs[i] = ptrs[i];
|
|
}
|
|
auto d_data = d_rank_data_base_++;
|
|
CUDACHECK(
|
|
cudaMemcpy(d_data, &data, sizeof(RankData), cudaMemcpyHostToDevice));
|
|
buffers_[ptrs[rank_]] = d_data;
|
|
}
|
|
|
|
// Note: when registering graph buffers, we intentionally choose to not
|
|
// deduplicate the addresses. That means if the allocator reuses some
|
|
// addresses, they will be registered again. This is to account for the
|
|
// remote possibility of different allocation patterns between ranks. For
|
|
// example, rank 1 may get the same input address for the second allreduce,
|
|
// but rank 2 got a different address. IPC handles have internal reference
|
|
// counting mechanism so overhead should be small.
|
|
void register_graph_buffers(
|
|
const std::vector<std::string>& handles,
|
|
const std::vector<std::vector<int64_t>>& offsets) {
|
|
auto num_buffers = graph_unreg_buffers_.size();
|
|
check_rank_data_capacity(num_buffers);
|
|
std::vector<RankData> rank_data(num_buffers);
|
|
for (int i = 0; i < num_buffers; i++) {
|
|
auto self_ptr = graph_unreg_buffers_[i];
|
|
auto& rd = rank_data[i];
|
|
for (int j = 0; j < world_size_; j++) {
|
|
if (j != rank_) {
|
|
char* handle =
|
|
open_ipc_handle(&handles[j][i * sizeof(cudaIpcMemHandle_t)]);
|
|
handle += offsets[j][i];
|
|
rd.ptrs[j] = handle;
|
|
} else {
|
|
rd.ptrs[j] = self_ptr;
|
|
}
|
|
}
|
|
}
|
|
CUDACHECK(cudaMemcpy(d_rank_data_base_, rank_data.data(),
|
|
sizeof(RankData) * num_buffers,
|
|
cudaMemcpyHostToDevice));
|
|
d_rank_data_base_ += num_buffers;
|
|
graph_unreg_buffers_.clear();
|
|
}
|
|
|
|
/**
|
|
* Performs allreduce, assuming input has already been registered.
|
|
*
|
|
* Block and grid default configs are results after careful grid search.
|
|
* Using 36 blocks give the best or close to the best runtime on the devices
|
|
* I tried: A100, A10, A30, T4, V100. You'll notice that NCCL kernels also
|
|
* only take a small amount of SMs. Not quite sure the underlying reason,
|
|
* but my guess is that too many SMs will cause contention on NVLink bus.
|
|
*/
|
|
template <typename T>
|
|
void allreduce(cudaStream_t stream, T* input, T* output, int size,
|
|
int threads = 512, int block_limit = defaultBlockLimit) {
|
|
auto d = packed_t<T>::P::size;
|
|
if (size % d != 0)
|
|
throw std::runtime_error(
|
|
"custom allreduce currently requires input length to be multiple "
|
|
"of " +
|
|
std::to_string(d));
|
|
if (block_limit > kMaxBlocks)
|
|
throw std::runtime_error("max supported block limit is " +
|
|
std::to_string(kMaxBlocks) + ". Got " +
|
|
std::to_string(block_limit));
|
|
|
|
RankData* ptrs;
|
|
cudaStreamCaptureStatus status;
|
|
CUDACHECK(cudaStreamIsCapturing(stream, &status));
|
|
if (status == cudaStreamCaptureStatusActive) {
|
|
ptrs = d_rank_data_base_ + graph_unreg_buffers_.size();
|
|
graph_unreg_buffers_.push_back(input);
|
|
} else {
|
|
auto it = buffers_.find(input);
|
|
if (it == buffers_.end())
|
|
throw std::runtime_error(
|
|
"buffer address " +
|
|
std::to_string(reinterpret_cast<uint64_t>(input)) +
|
|
" is not registered!");
|
|
ptrs = it->second;
|
|
}
|
|
|
|
size /= d;
|
|
auto bytes = size * sizeof(typename packed_t<T>::P);
|
|
int blocks = std::min(block_limit, (size + threads - 1) / threads);
|
|
#define KL(ngpus, name) \
|
|
name<T, ngpus><<<blocks, threads, 0, stream>>>(ptrs, sg_, self_sg_, output, \
|
|
rank_, size);
|
|
#define REDUCE_CASE(ngpus) \
|
|
case ngpus: { \
|
|
if (world_size_ == 2) { \
|
|
KL(ngpus, cross_device_reduce_1stage); \
|
|
} else if (fully_connected_) { \
|
|
if ((world_size_ <= 4 && bytes < 512 * 1024) || \
|
|
(world_size_ <= 8 && bytes < 256 * 1024)) { \
|
|
KL(ngpus, cross_device_reduce_1stage); \
|
|
} else { \
|
|
KL(ngpus, cross_device_reduce_2stage); \
|
|
} \
|
|
} \
|
|
break; \
|
|
}
|
|
|
|
switch (world_size_) {
|
|
REDUCE_CASE(2)
|
|
REDUCE_CASE(4)
|
|
REDUCE_CASE(6)
|
|
REDUCE_CASE(8)
|
|
default:
|
|
throw std::runtime_error(
|
|
"custom allreduce only supports num gpus in (2,4,6,8). Actual "
|
|
"num "
|
|
"gpus = " +
|
|
std::to_string(world_size_));
|
|
}
|
|
#undef REDUCE_CASE
|
|
#undef KL
|
|
}
|
|
|
|
~CustomAllreduce() {
|
|
for (auto [_, ptr] : ipc_handles_) {
|
|
CUDACHECK(cudaIpcCloseMemHandle(ptr));
|
|
}
|
|
}
|
|
};
|
|
|
|
/**
|
|
* To inspect PTX/SASS, copy paste this header file to compiler explorer and
|
|
add a template instantiation:
|
|
* template void vllm::CustomAllreduce::allreduce<half>(cudaStream_t, half *,
|
|
half *, int, int, int);
|
|
*/
|
|
} // namespace vllm |