483 lines
17 KiB
Plaintext
483 lines
17 KiB
Plaintext
#pragma once
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#include <cuda.h>
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#include <cuda_bf16.h>
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#include <cuda_fp16.h>
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#include <cuda_runtime.h>
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#include <iostream>
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#include <limits>
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#include <map>
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#include <unordered_map>
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#include <vector>
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#define CUDACHECK(cmd) \
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do { \
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cudaError_t e = cmd; \
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if (e != cudaSuccess) { \
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printf("Failed: Cuda error %s:%d '%s'\n", __FILE__, __LINE__, \
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cudaGetErrorString(e)); \
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exit(EXIT_FAILURE); \
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} \
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} while (0)
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namespace vllm {
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constexpr int kMaxBlocks = 64;
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// note: we don't want to use atomics for signals because peer atomics are no
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// supported on PCIe links
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struct Signal {
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alignas(128) uint32_t start[kMaxBlocks][8];
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alignas(128) uint32_t end[kMaxBlocks][8];
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};
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struct __align__(16) RankData { const void* __restrict__ ptrs[8]; };
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struct __align__(16) RankSignals { volatile Signal* signals[8]; };
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// like std::array, but aligned
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template <typename T, int sz>
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struct __align__(alignof(T) * sz) array_t {
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T data[sz];
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using type = T;
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static constexpr int size = sz;
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};
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// use packed type to maximize memory efficiency
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// goal: generate ld.128 and st.128 instructions
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template <typename T>
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struct packed_t {
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// the (P)acked type for load/store
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using P = array_t<T, 16 / sizeof(T)>;
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// the (A)ccumulator type for reduction
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using A = array_t<float, 16 / sizeof(T)>;
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};
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#define DINLINE __device__ __forceinline__
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// scalar cast functions
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DINLINE float upcast_s(half val) { return __half2float(val); }
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template <typename T>
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DINLINE T downcast_s(float val);
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template <>
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DINLINE half downcast_s(float val) {
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return __float2half(val);
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}
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// scalar add functions
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// for some reason when compiling with Pytorch, the + operator for half and
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// bfloat is disabled so we call the intrinsics directly
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DINLINE half& assign_add(half& a, half b) {
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a = __hadd(a, b);
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return a;
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}
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DINLINE float& assign_add(float& a, float b) { return a += b; }
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#if (__CUDA_ARCH__ >= 800 || !defined(__CUDA_ARCH__))
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DINLINE float upcast_s(nv_bfloat16 val) { return __bfloat162float(val); }
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template <>
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DINLINE nv_bfloat16 downcast_s(float val) {
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return __float2bfloat16(val);
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}
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DINLINE nv_bfloat16& assign_add(nv_bfloat16& a, nv_bfloat16 b) {
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a = __hadd(a, b);
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return a;
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}
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#endif
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template <typename T, int N>
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DINLINE array_t<T, N>& packed_assign_add(array_t<T, N>& a, array_t<T, N> b) {
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#pragma unroll
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for (int i = 0; i < N; i++) {
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assign_add(a.data[i], b.data[i]);
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}
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return a;
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}
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template <typename T, int N>
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DINLINE array_t<float, N> upcast(array_t<T, N> val) {
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if constexpr (std::is_same<T, float>::value) {
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return val;
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} else {
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array_t<float, N> out;
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#pragma unroll
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for (int i = 0; i < N; i++) {
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out.data[i] = upcast_s(val.data[i]);
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}
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return out;
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}
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}
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template <typename O>
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DINLINE O downcast(array_t<float, O::size> val) {
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if constexpr (std::is_same<typename O::type, float>::value) {
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return val;
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} else {
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O out;
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#pragma unroll
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for (int i = 0; i < O::size; i++) {
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out.data[i] = downcast_s<typename O::type>(val.data[i]);
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}
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return out;
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}
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}
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// This function is meant to be used as the first synchronization in the all
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// reduce kernel. Thus, it doesn't need to make any visibility guarantees for
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// prior memory accesses. Note: volatile writes will not be reordered against
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// other volatile writes.
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template <int ngpus>
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DINLINE void start_sync(const RankSignals& sg, volatile Signal* self_sg,
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int rank) {
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if (threadIdx.x < ngpus) {
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// reset flag for next time
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self_sg->end[blockIdx.x][threadIdx.x] = 0;
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// simultaneously write to the corresponding flag of all ranks.
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// Latency = 1 p2p write
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sg.signals[threadIdx.x]->start[blockIdx.x][rank] = 1;
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// wait until we got true from all ranks
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while (!self_sg->start[blockIdx.x][threadIdx.x]);
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}
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__syncthreads();
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}
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// This function is meant to be used as the second or the final synchronization
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// barrier in the all reduce kernel. If it's the final synchronization barrier,
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// we don't need to make any visibility guarantees for prior memory accesses.
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template <int ngpus, bool final_sync = false>
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DINLINE void end_sync(const RankSignals& sg, volatile Signal* self_sg,
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int rank) {
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__syncthreads();
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// eliminate the case that prior writes are not visible after signals become
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// visible. Note that I did not managed to make this happen through a lot of
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// testing. Might be the case that hardware provides stronger guarantee than
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// the memory model.
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if constexpr (!final_sync) __threadfence_system();
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if (threadIdx.x < ngpus) {
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// reset flag for next time
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self_sg->start[blockIdx.x][threadIdx.x] = 0;
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// simultaneously write to the corresponding flag of all ranks.
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// Latency = 1 p2p write
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sg.signals[threadIdx.x]->end[blockIdx.x][rank] = 1;
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// wait until we got true from all ranks
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while (!self_sg->end[blockIdx.x][threadIdx.x]);
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}
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if constexpr (!final_sync) __syncthreads();
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}
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template <typename P, int ngpus, typename A>
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DINLINE P packed_reduce(const P* ptrs[], int idx) {
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A tmp = upcast(ptrs[0][idx]);
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#pragma unroll
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for (int i = 1; i < ngpus; i++) {
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packed_assign_add(tmp, upcast(ptrs[i][idx]));
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}
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return downcast<P>(tmp);
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}
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template <typename T, int ngpus>
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__global__ void __launch_bounds__(512, 1)
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cross_device_reduce_1stage(RankData* _dp, RankSignals sg,
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volatile Signal* self_sg, T* __restrict__ result,
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int rank, int size) {
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using P = typename packed_t<T>::P;
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using A = typename packed_t<T>::A;
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// note: we don't reorder the address so the accumulation order is the same
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// for all ranks, ensuring bitwise identical results
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auto dp = *_dp;
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start_sync<ngpus>(sg, self_sg, rank);
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// do the actual reduction
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for (int idx = blockIdx.x * blockDim.x + threadIdx.x; idx < size;
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idx += gridDim.x * blockDim.x) {
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((P*)result)[idx] = packed_reduce<P, ngpus, A>((const P**)&dp.ptrs[0], idx);
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}
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end_sync<ngpus, true>(sg, self_sg, rank);
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}
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template <typename P>
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DINLINE P* get_tmp_buf(volatile Signal* sg) {
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return (P*)(((Signal*)sg) + 1);
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}
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template <typename T, int ngpus>
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__global__ void __launch_bounds__(512, 1)
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cross_device_reduce_2stage(RankData* _dp, RankSignals sg,
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volatile Signal* self_sg, T* __restrict__ result,
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int rank, int size) {
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int tid = blockIdx.x * blockDim.x + threadIdx.x;
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int stride = gridDim.x * blockDim.x;
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using P = typename packed_t<T>::P;
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using A = typename packed_t<T>::A;
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int part = size / ngpus;
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int start = rank * part;
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int end = rank == ngpus - 1 ? size : start + part;
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int largest_part = part + size % ngpus;
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const P* ptrs[ngpus];
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P* tmps[ngpus];
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#pragma unroll
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for (int i = 0; i < ngpus; i++) {
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int target = (rank + i) % ngpus;
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ptrs[i] = (const P*)_dp->ptrs[target];
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tmps[i] = get_tmp_buf<P>(sg.signals[target]);
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}
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auto tmp_out = tmps[0];
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start_sync<ngpus>(sg, self_sg, rank);
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// stage 1: reduce scatter
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for (int idx = start + tid; idx < end; idx += stride) {
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tmp_out[idx - start] = packed_reduce<P, ngpus, A>(ptrs, idx);
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}
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end_sync<ngpus>(sg, self_sg, rank);
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// stage 2: allgather. Note: it's important to match the tid between
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// the two stages, because visibility across devices is only guaranteed
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// between threads that have the same tid. If thread i computes the sum of
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// start + i in the first stage, then thread i also gathers start + i from all
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// ranks.
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for (int idx = tid; idx < largest_part; idx += stride) {
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#pragma unroll
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for (int i = 0; i < ngpus; i++) {
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int gather_from_rank = ((rank + i) % ngpus);
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if (gather_from_rank == ngpus - 1 || idx < part) {
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int dst_idx = gather_from_rank * part + idx;
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((P*)result)[dst_idx] = tmps[i][idx];
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}
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}
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}
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}
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using IPC_KEY = std::array<uint8_t, sizeof(cudaIpcMemHandle_t)>;
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static_assert(sizeof(IPC_KEY) == sizeof(cudaIpcMemHandle_t));
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static_assert(alignof(IPC_KEY) == alignof(cudaIpcMemHandle_t));
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class CustomAllreduce {
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public:
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int rank_;
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int world_size_;
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bool full_nvlink_;
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// below are device pointers
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RankSignals sg_;
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std::unordered_map<void*, RankData*> buffers_;
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Signal* self_sg_;
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// stores the registered device pointers from all ranks
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RankData *d_rank_data_base_, *d_rank_data_end_;
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std::vector<void*> graph_unreg_buffers_;
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// a map from IPC handles to opened IPC pointers
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std::map<IPC_KEY, char*> ipc_handles_;
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/**
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* meta is a pointer to device metadata and temporary buffer for allreduce.
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*
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* There's a total of sizeof(Signal) of prefix before the actual data,
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* so meta + 1 points to actual temporary buffer.
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*
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* note: this class does not own any device memory. Any required buffers
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* are passed in from the constructor
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*/
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CustomAllreduce(Signal* meta, void* rank_data, size_t rank_data_sz,
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const cudaIpcMemHandle_t* handles,
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const std::vector<int64_t>& offsets, int rank,
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bool full_nvlink = true)
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: rank_(rank),
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world_size_(offsets.size()),
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full_nvlink_(full_nvlink),
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self_sg_(meta),
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d_rank_data_base_(reinterpret_cast<RankData*>(rank_data)),
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d_rank_data_end_(d_rank_data_base_ + rank_data_sz / sizeof(RankData)) {
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for (int i = 0; i < world_size_; i++) {
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Signal* rank_sg;
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if (i != rank_) {
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char* handle = open_ipc_handle(&handles[i]);
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handle += offsets[i];
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rank_sg = (Signal*)handle;
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} else {
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rank_sg = self_sg_;
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}
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sg_.signals[i] = rank_sg;
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}
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}
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char* open_ipc_handle(const void* ipc_handle) {
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auto [it, new_handle] =
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ipc_handles_.insert({*((IPC_KEY*)ipc_handle), nullptr});
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if (new_handle) {
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char* ipc_ptr;
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CUDACHECK(cudaIpcOpenMemHandle((void**)&ipc_ptr,
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*((const cudaIpcMemHandle_t*)ipc_handle),
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cudaIpcMemLazyEnablePeerAccess));
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it->second = ipc_ptr;
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}
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return it->second;
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}
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std::pair<std::vector<uint8_t>, std::vector<int64_t>>
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get_graph_buffer_ipc_meta() {
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auto num_buffers = graph_unreg_buffers_.size();
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auto handle_sz = sizeof(cudaIpcMemHandle_t);
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std::vector<uint8_t> handles(handle_sz * num_buffers, 0);
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std::vector<int64_t> offsets(num_buffers);
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for (int i = 0; i < num_buffers; i++) {
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auto ptr = graph_unreg_buffers_[i];
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void* base_ptr;
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// note: must share the base address of each allocation, or we get wrong
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// address
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if (cuPointerGetAttribute(&base_ptr,
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CU_POINTER_ATTRIBUTE_RANGE_START_ADDR,
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(CUdeviceptr)ptr) != CUDA_SUCCESS)
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throw std::runtime_error("failed to get pointer attr");
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CUDACHECK(cudaIpcGetMemHandle(
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(cudaIpcMemHandle_t*)&handles[i * handle_sz], base_ptr));
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offsets[i] = ((char*)ptr) - ((char*)base_ptr);
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}
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return std::make_pair(handles, offsets);
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}
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void check_rank_data_capacity(size_t num = 1) {
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if (d_rank_data_base_ + num > d_rank_data_end_)
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throw std::runtime_error(
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"Rank data buffer is overflowed by " +
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std::to_string(d_rank_data_base_ + num - d_rank_data_end_));
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}
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void register_buffer(const std::vector<std::string>& handles,
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const std::vector<int64_t>& offsets, void* self) {
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check_rank_data_capacity();
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RankData data;
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for (int i = 0; i < world_size_; i++) {
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if (i != rank_) {
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char* handle = open_ipc_handle(handles[i].data());
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handle += offsets[i];
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data.ptrs[i] = handle;
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} else {
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data.ptrs[i] = self;
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}
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}
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auto d_data = d_rank_data_base_++;
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CUDACHECK(
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cudaMemcpy(d_data, &data, sizeof(RankData), cudaMemcpyHostToDevice));
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buffers_[self] = d_data;
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}
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// note: when registering graph buffers, we intentionally choose to not
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// deduplicate the addresses. That means if the allocator reuses some
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// addresses, they will be registered again. This is to account for the remote
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// possibility of different allocation patterns between ranks. For example,
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// rank 1 may get the same input address for the second allreduce, but rank 2
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// got a different address. IPC handles have internal reference counting
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// mechanism so overhead should be small.
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void register_graph_buffers(
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const std::vector<std::string>& handles,
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const std::vector<std::vector<int64_t>>& offsets) {
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auto num_buffers = graph_unreg_buffers_.size();
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check_rank_data_capacity(num_buffers);
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std::vector<RankData> rank_data(num_buffers);
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for (int i = 0; i < num_buffers; i++) {
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auto self_ptr = graph_unreg_buffers_[i];
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auto& rd = rank_data[i];
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for (int j = 0; j < world_size_; j++) {
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if (j != rank_) {
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char* handle =
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open_ipc_handle(&handles[j][i * sizeof(cudaIpcMemHandle_t)]);
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handle += offsets[j][i];
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rd.ptrs[j] = handle;
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} else {
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rd.ptrs[j] = self_ptr;
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}
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}
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}
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CUDACHECK(cudaMemcpy(d_rank_data_base_, rank_data.data(),
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sizeof(RankData) * num_buffers,
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cudaMemcpyHostToDevice));
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d_rank_data_base_ += num_buffers;
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graph_unreg_buffers_.clear();
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}
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/**
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* This is the result after careful grid search. Using 36 blocks give the best
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* or close to the best runtime on the devices I tried: A100, A10, A30, T4,
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* V100. You'll notice that NCCL kernels also only take a small amount of SMs.
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* Not quite sure the underlying reason, but my guess is that too many SMs
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* will cause contention on NVLink bus.
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*/
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template <typename T>
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void allreduce(cudaStream_t stream, T* input, T* output, int size,
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int threads = 512, int block_limit = 36) {
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auto d = packed_t<T>::P::size;
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if (size % d != 0)
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throw std::runtime_error(
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"custom allreduce currently requires input length to be multiple "
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"of " +
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std::to_string(d));
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if (block_limit > kMaxBlocks)
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throw std::runtime_error("max supported block limit is " +
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std::to_string(kMaxBlocks) + ". Got " +
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std::to_string(block_limit));
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RankData* ptrs;
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cudaStreamCaptureStatus status;
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CUDACHECK(cudaStreamIsCapturing(stream, &status));
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if (status == cudaStreamCaptureStatusActive) {
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ptrs = d_rank_data_base_ + graph_unreg_buffers_.size();
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graph_unreg_buffers_.push_back(input);
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} else {
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auto it = buffers_.find(input);
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if (it == buffers_.end())
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throw std::runtime_error(
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"buffer address " +
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std::to_string(reinterpret_cast<uint64_t>(input)) +
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" is not registered!");
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ptrs = it->second;
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}
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size /= d;
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auto bytes = size * sizeof(typename packed_t<T>::P);
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int blocks = std::min(block_limit, (size + threads - 1) / threads);
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#define KL(ngpus, name) \
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name<T, ngpus><<<blocks, threads, 0, stream>>>(ptrs, sg_, self_sg_, output, \
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rank_, size);
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#define REDUCE_CASE(ngpus) \
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case ngpus: { \
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if (world_size_ == 2) { \
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KL(ngpus, cross_device_reduce_1stage); \
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} else if (full_nvlink_) { \
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if ((world_size_ <= 4 && bytes < 512 * 1024) || \
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(world_size_ <= 8 && bytes < 256 * 1024)) { \
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KL(ngpus, cross_device_reduce_1stage); \
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} else { \
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KL(ngpus, cross_device_reduce_2stage); \
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} \
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} \
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break; \
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}
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switch (world_size_) {
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REDUCE_CASE(2)
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REDUCE_CASE(4)
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REDUCE_CASE(6)
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REDUCE_CASE(8)
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default:
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throw std::runtime_error(
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"custom allreduce only supports num gpus in (2,4,6,8). Actual num "
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"gpus = " +
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|
std::to_string(world_size_));
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|
}
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#undef REDUCE_CASE
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|
#undef KL
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|
}
|
|
|
|
~CustomAllreduce() {
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|
for (auto [_, ptr] : ipc_handles_) {
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|
CUDACHECK(cudaIpcCloseMemHandle(ptr));
|
|
}
|
|
}
|
|
};
|
|
/**
|
|
* To inspect PTX/SASS, copy paste this header file to compiler explorer and add
|
|
a template instantiation:
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|
* template void vllm::CustomAllreduce::allreduce<half>(cudaStream_t, half *,
|
|
half *, int, int, int);
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|
*/
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|
} // namespace vllm
|