yihong
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6342adc438
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fix: support clang17 for macos and fix the real libomp (#16086)
Signed-off-by: yihong0618 <zouzou0208@gmail.com>
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2025-04-05 11:00:12 +00:00 |
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Li, Jiang
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550b2801ad
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[CPU][Bugfix] Using custom allreduce for CPU backend (#15934)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2025-04-02 07:46:47 -07:00 |
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Thien Tran
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4f044b1d67
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[Kernel][CPU] CPU MLA (#14744)
Signed-off-by: Thien Tran <gau.nernst@yahoo.com.sg>
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2025-03-25 09:34:59 +00:00 |
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Li, Jiang
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ff47aab056
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[CPU] Upgrade CPU backend to torch-2.6 (#13381)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
Co-authored-by: Isotr0py <2037008807@qq.com>
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2025-03-12 10:41:13 +00:00 |
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Dilip Gowda Bhagavan
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ada19210a3
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Adding cpu inference with VXE ISA for s390x architecture (#12613)
Signed-off-by: Dilip Gowda Bhagavan <dilip.bhagavan@ibm.com>
Signed-off-by: Rishika Kedia <rishika.kedia@in.ibm.com>
Co-authored-by: Rishika Kedia <rishika.kedia@in.ibm.com>
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2025-03-06 08:40:53 -08:00 |
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Wallas Henrique
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cfd3219f58
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[Hardware][Apple] Native support for macOS Apple Silicon (#11696)
Signed-off-by: Wallas Santos <wallashss@ibm.com>
Co-authored-by: Michael Goin <michael@neuralmagic.com>
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2025-01-08 16:35:49 +08:00 |
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Sanket Kale
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a6760f6456
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[Feature] vLLM ARM Enablement for AARCH64 CPUs (#9228)
Signed-off-by: Sanket Kale <sanketk.kale@fujitsu.com>
Co-authored-by: Sanket Kale <sanketk.kale@fujitsu.com>
Co-authored-by: mgoin <michael@neuralmagic.com>
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2024-11-25 18:32:39 -08:00 |
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Manjul Mohan
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1ea291a417
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Fix: Build error seen on Power Architecture (#10421)
Signed-off-by: Manjul Mohan <manjul.mohan@ibm.com>
Signed-off-by: B-201 <Joy25810@foxmail.com>
Signed-off-by: Isotr0py <2037008807@qq.com>
Signed-off-by: youkaichao <youkaichao@gmail.com>
Signed-off-by: ismael-dm <ismaeldm99@gmail.com>
Signed-off-by: Andrew Nesbitt <andrewnez@gmail.com>
Signed-off-by: mgoin <michael@neuralmagic.com>
Signed-off-by: yan ma <yan.ma@intel.com>
Signed-off-by: Angus Wang <wangjadehao@gmail.com>
Signed-off-by: Lucas Wilkinson <lwilkinson@neuralmagic.com>
Signed-off-by: rickyx <rickyx@anyscale.com>
Signed-off-by: Jee Jee Li <pandaleefree@gmail.com>
Signed-off-by: Mengqing Cao <cmq0113@163.com>
Signed-off-by: Travis Johnson <tsjohnso@us.ibm.com>
Co-authored-by: Manjul Mohan manjul.mohan@ibm.com <manjulmohan@ltcd97-lp2.aus.stglabs.ibm.com>
Co-authored-by: B-201 <Joy25810@foxmail.com>
Co-authored-by: Isotr0py <2037008807@qq.com>
Co-authored-by: youkaichao <youkaichao@gmail.com>
Co-authored-by: ismael-dm <ismaeldm99@gmail.com>
Co-authored-by: Andrew Nesbitt <andrewnez@gmail.com>
Co-authored-by: Michael Goin <michael@neuralmagic.com>
Co-authored-by: Yan Ma <yan.ma@intel.com>
Co-authored-by: Angus Wang <wangjadehao@gmail.com>
Co-authored-by: Lucas Wilkinson <LucasWilkinson@users.noreply.github.com>
Co-authored-by: Ricky Xu <rickyx@anyscale.com>
Co-authored-by: Kevin H. Luu <kevin@anyscale.com>
Co-authored-by: Jee Jee Li <pandaleefree@gmail.com>
Co-authored-by: Mengqing Cao <cmq0113@163.com>
Co-authored-by: Travis Johnson <tsjohnso@us.ibm.com>
Co-authored-by: Russell Bryant <rbryant@redhat.com>
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2024-11-19 09:34:57 -08:00 |
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Li, Jiang
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a6f332d0d9
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[Hardware][CPU][bugfix] Fix half dtype support on AVX2-only target (#10108)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2024-11-07 18:42:50 +08:00 |
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Li, Jiang
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a4b3e0c1e9
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[Hardware][CPU] Update torch 2.5 (#9911)
Signed-off-by: jiang1.li <jiang1.li@intel.com>
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2024-11-07 04:43:08 +00:00 |
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Li, Jiang
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5eda21e773
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[Hardware][CPU] compressed-tensor INT8 W8A8 AZP support (#9344)
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2024-10-17 12:21:04 -04:00 |
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Varad Ahirwadkar
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e5dc713c23
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[Hardware][PowerPC] Make oneDNN dependency optional for Power (#9039)
Signed-off-by: Varad Ahirwadkar <varad.ahirwadkar1@ibm.com>
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2024-10-04 17:24:42 +00:00 |
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Luka Govedič
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57a0702e63
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[Bugfix] Fix CPU CMake build (#8723)
Co-authored-by: Yuan <yuan.zhou@intel.com>
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2024-09-22 20:40:46 -07:00 |
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Li, Jiang
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0b952af458
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[Hardware][Intel] Support compressed-tensor W8A8 for CPU backend (#7257)
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2024-09-11 09:46:46 -07:00 |
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Lucas Wilkinson
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a8d604ca2a
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[Misc] Disambiguate quantized types via a new ScalarType (#6396)
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2024-08-02 13:51:58 -07:00 |
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Li, Jiang
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3bbb4936dc
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[Hardware] [Intel] Enable Multiprocessing and tensor parallel in CPU backend and update documentation (#6125)
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2024-07-26 13:50:10 -07:00 |
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Chip Kerchner
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38a1674abb
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Support CPU inference with VSX PowerPC ISA (#5652)
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2024-06-26 21:53:04 +00:00 |
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Jie Fu (傅杰)
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ab66536dbf
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[CI/BUILD] Support non-AVX512 vLLM building and testing (#5574)
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2024-06-17 14:36:10 -04:00 |
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Jie Fu (傅杰)
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cd9c0d65d9
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[Hardware][Intel] Support CPU inference with AVX2 ISA (#5452)
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2024-06-13 17:22:24 -06:00 |
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bnellnm
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5467ac3196
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[Kernel][Misc] Use TORCH_LIBRARY instead of PYBIND11_MODULE for custom ops (#5047)
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2024-06-09 16:23:30 -04:00 |
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bigPYJ1151
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0e3f06fe9c
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[Hardware][Intel] Add CPU inference backend (#3634)
Co-authored-by: Kunshang Ji <kunshang.ji@intel.com>
Co-authored-by: Yuan Zhou <yuan.zhou@intel.com>
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2024-04-01 22:07:30 -07:00 |
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